arch/alpha/kernel/core_cia.c
Source file repositories/reference/linux-study-clean/arch/alpha/kernel/core_cia.c
File Facts
- System
- Linux kernel
- Corpus path
arch/alpha/kernel/core_cia.c- Extension
.c- Size
- 33449 bytes
- Lines
- 1214
- Domain
- Architecture Layer
- Bucket
- arch/alpha
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/io.hasm/core_cia.hlinux/types.hlinux/pci.hlinux/sched.hlinux/init.hlinux/memblock.hasm/ptrace.hasm/mce.hproto.hpci_impl.h
Detected Declarations
function Ruslingfunction conf_readfunction conf_writefunction cia_read_configfunction cia_write_configfunction cia_pci_tbifunction chipfunction cia_prepare_tbia_workaroundfunction verify_tb_operationfunction cia_save_srm_settingsfunction cia_restore_srm_settingsfunction do_init_archfunction cia_init_archfunction pyxis_init_archfunction cia_kill_archfunction cia_init_pcifunction cia_pci_clr_errfunction cia_decode_pci_errorfunction cia_decode_mem_errorfunction cia_decode_ecc_errorfunction cia_decode_parity_errorfunction cia_decode_mchkfunction cia_machine_check
Annotated Snippet
if (temp & 1) {
use_tbia_try2 = 1;
printk("pci: failed tbia test; workaround available\n");
} else {
printk("pci: passed tbia test\n");
}
}
/* Fourth, verify the TLB snoops the EV5's caches when
doing a tlb fill. */
data0 = 0x5adda15e;
page[0] = data0;
arena->ptes[4] = pte0;
mcheck_expected(0) = 1;
mcheck_taken(0) = 0;
mb();
temp = cia_readl(bus_addr + 4*PAGE_SIZE);
mb();
mcheck_expected(0) = 0;
mb();
if (mcheck_taken(0)) {
printk("pci: failed pte write cache snoop test (mcheck)\n");
goto failed;
}
if (temp != data0) {
printk("pci: failed pte write cache snoop test "
"(%#x != %#x)\n", temp, data0);
goto failed;
}
printk("pci: passed pte write cache snoop test\n");
/* Fifth, verify that a previously invalid PTE entry gets
filled from the page table. */
data0 = 0xabcdef12;
page[0] = data0;
arena->ptes[5] = pte0;
mcheck_expected(0) = 1;
mcheck_taken(0) = 0;
mb();
temp = cia_readl(bus_addr + 5*PAGE_SIZE);
mb();
mcheck_expected(0) = 0;
mb();
if (mcheck_taken(0)) {
printk("pci: failed valid tag invalid pte reload test "
"(mcheck; workaround available)\n");
/* Work around this bug by aligning new allocations
on 4 page boundaries. */
arena->align_entry = 4;
} else if (temp != data0) {
printk("pci: failed valid tag invalid pte reload test "
"(%#x != %#x)\n", temp, data0);
goto failed;
} else {
printk("pci: passed valid tag invalid pte reload test\n");
}
/* Sixth, verify machine checks are working. Test invalid
pte under the same valid tag as we used above. */
mcheck_expected(0) = 1;
mcheck_taken(0) = 0;
mb();
temp = cia_readl(bus_addr + 6*PAGE_SIZE);
mb();
mcheck_expected(0) = 0;
mb();
printk("pci: %s pci machine check test\n",
mcheck_taken(0) ? "passed" : "failed");
/* Clean up after the tests. */
arena->ptes[4] = 0;
arena->ptes[5] = 0;
if (use_tbia_try2) {
alpha_mv.mv_pci_tbi = cia_pci_tbi_try2;
/* Tags 0-3 must be disabled if we use this workaround. */
wmb();
*(vip)CIA_IOC_TB_TAGn(0) = 2;
*(vip)CIA_IOC_TB_TAGn(1) = 2;
*(vip)CIA_IOC_TB_TAGn(2) = 2;
*(vip)CIA_IOC_TB_TAGn(3) = 2;
printk("pci: tbia workaround enabled\n");
}
alpha_mv.mv_pci_tbi(arena->hose, 0, -1);
Annotation
- Immediate include surface: `asm/io.h`, `asm/core_cia.h`, `linux/types.h`, `linux/pci.h`, `linux/sched.h`, `linux/init.h`, `linux/memblock.h`, `asm/ptrace.h`.
- Detected declarations: `function Rusling`, `function conf_read`, `function conf_write`, `function cia_read_config`, `function cia_write_config`, `function cia_pci_tbi`, `function chip`, `function cia_prepare_tbia_workaround`, `function verify_tb_operation`, `function cia_save_srm_settings`.
- Atlas domain: Architecture Layer / arch/alpha.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.