arch/arc/boot/dts/axs10x_mb.dtsi

Source file repositories/reference/linux-study-clean/arch/arc/boot/dts/axs10x_mb.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arc/boot/dts/axs10x_mb.dtsi
Extension
.dtsi
Size
7207 bytes
Lines
331
Domain
Architecture Layer
Bucket
arch/arc
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Support for peripherals on the AXS10x mainboard
 *
 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
 */

/ {
	aliases {
		ethernet = &gmac;
	};

	axs10x_mb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
		interrupt-parent = <&mb_intc>;

		creg_rst: reset-controller@11220 {
			compatible = "snps,axs10x-reset";
			#reset-cells = <1>;
			reg = <0x11220 0x4>;
		};

		i2sclk: i2sclk@100a0 {
			compatible = "snps,axs10x-i2s-pll-clock";
			reg = <0x100a0 0x10>;
			clocks = <&i2spll_clk>;
			#clock-cells = <0>;
		};

		clocks {
			i2spll_clk: i2spll_clk {
				compatible = "fixed-clock";
				clock-frequency = <27000000>;
				#clock-cells = <0>;
			};

			i2cclk: i2cclk {
				compatible = "fixed-clock";
				clock-frequency = <50000000>;
				#clock-cells = <0>;
			};

			apbclk: apbclk {
				compatible = "fixed-clock";
				clock-frequency = <50000000>;
				#clock-cells = <0>;
			};

			mmcclk: mmcclk {
				compatible = "fixed-clock";
				/*
				 * DW sdio controller has external ciu clock divider
				 * controlled via register in SDIO IP. It divides
				 * sdio_ref_clk (which comes from CGU) by 16 for
				 * default. So default mmcclk clock (which comes
				 * to sdk_in) is 25000000 Hz.
				 */
				clock-frequency = <25000000>;
				#clock-cells = <0>;
			};
		};

		pguclk: pguclk@10080 {
			compatible = "snps,axs10x-pgu-pll-clock";
			reg = <0x10080 0x10>, <0x110 0x10>;
			#clock-cells = <0>;
			clocks = <&input_clk>;

Annotation

Implementation Notes