arch/arm/boot/dts/actions/owl-s500.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/actions/owl-s500.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/actions/owl-s500.dtsi- Extension
.dtsi- Size
- 8817 bytes
- Lines
- 339
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/actions,s500-cmu.hdt-bindings/gpio/gpio.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/power/owl-s500-powergate.hdt-bindings/reset/actions,s500-reset.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Actions Semi S500 SoC
*
* Copyright (c) 2016-2017 Andreas Färber
*/
#include <dt-bindings/clock/actions,s500-cmu.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/owl-s500-powergate.h>
#include <dt-bindings/reset/actions,s500-reset.h>
/ {
compatible = "actions,s500";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
aliases {
};
chosen {
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x0>;
enable-method = "actions,s500-smp";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x1>;
enable-method = "actions,s500-smp";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x2>;
enable-method = "actions,s500-smp";
power-domains = <&sps S500_PD_CPU2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x3>;
enable-method = "actions,s500-smp";
power-domains = <&sps S500_PD_CPU3>;
};
};
arm-pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
hosc: hosc {
Annotation
- Immediate include surface: `dt-bindings/clock/actions,s500-cmu.h`, `dt-bindings/gpio/gpio.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/power/owl-s500-powergate.h`, `dt-bindings/reset/actions,s500-reset.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.