arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts- Extension
.dts- Size
- 3146 bytes
- Lines
- 101
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
sun8i-h2-plus-orangepi-zero.dts
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include "sun8i-h2-plus-orangepi-zero.dts"
/delete-node/ ®_vcc_wifi;
/ {
model = "Xunlong Orange Pi R1";
compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus";
/*
* Ths pin of this regulator is the same with the Wi-Fi extra
* regulator on the original Zero. However it's used for USB
* Ethernet rather than the Wi-Fi now.
*/
reg_vcc_usb_eth: reg-vcc-usb-ethernet {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-usb-ethernet";
enable-active-high;
gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
};
aliases {
ethernet1 = &rtl8189etv;
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "mxicy,mx25l12805d", "jedec,spi-nor";
};
};
&ohci1 {
/*
* RTL8152B USB-Ethernet adapter is connected to USB1,
* and it's a USB 2.0 device. So the OHCI1 controller
* can be left disabled.
*/
status = "disabled";
};
&mmc1 {
vmmc-supply = <®_vcc3v3>;
vqmmc-supply = <®_vcc3v3>;
rtl8189etv: wifi@1 {
reg = <1>;
};
};
&usbphy {
usb1_vbus-supply = <®_vcc_usb_eth>;
};
Annotation
- Immediate include surface: `sun8i-h2-plus-orangepi-zero.dts`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.