arch/arm/boot/dts/amazon/alpine.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/amazon/alpine.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/amazon/alpine.dtsi- Extension
.dtsi- Size
- 4627 bytes
- Lines
- 176
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
/* SOC compatibility */
compatible = "al,alpine";
memory {
device_type = "memory";
reg = <0 0 0 0>;
};
/* CPU Configuration */
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "al,alpine-smp";
cpu@0 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <0>;
clock-frequency = <1700000000>;
};
cpu@1 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <1>;
clock-frequency = <1700000000>;
};
cpu@2 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <2>;
clock-frequency = <1700000000>;
};
cpu@3 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <3>;
clock-frequency = <1700000000>;
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
arch-timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <50000000>;
};
/* Interrupt Controller */
gic: interrupt-controller@fb001000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.