arch/arm/boot/dts/amlogic/meson8b.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/amlogic/meson8b.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/amlogic/meson8b.dtsi
Extension
.dtsi
Size
17675 bytes
Lines
791
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2015 Endless Mobile, Inc.
 * Author: Carlo Caione <carlo@endlessm.com>
 */

#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8b-gpio.h>
#include <dt-bindings/power/meson8-power.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#include <dt-bindings/thermal/thermal.h>
#include "meson.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
			reg = <0x200>;
			enable-method = "amlogic,meson8b-smp";
			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu1: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
			reg = <0x201>;
			enable-method = "amlogic,meson8b-smp";
			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu2: cpu@202 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
			reg = <0x202>;
			enable-method = "amlogic,meson8b-smp";
			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu3: cpu@203 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
			reg = <0x203>;
			enable-method = "amlogic,meson8b-smp";
			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};
	};

	cpu_opp_table: opp-table {

Annotation

Implementation Notes