arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi
Extension
.dtsi
Size
5446 bytes
Lines
221
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include "arm-realview-eb.dtsi"

/*
 * This is the common include file for all MPCore variants of the
 * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B
 * and Cortex-A9 MPCore.
 */
/ {
	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,realview-eb-soc", "simple-bus";
		regmap = <&syscon>;
		ranges;

		/* Primary interrupt controller in the test chip */
		intc: interrupt-controller@1f000100 {
			compatible = "arm,eb11mp-gic";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0x1f001000 0x1000>,
			      <0x1f000100 0x100>;
		};

		/* Secondary interrupt controller on the FPGA */
		intc_second: interrupt-controller@10040000 {
			compatible = "arm,pl390";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0x10041000 0x1000>,
			      <0x10040000 0x100>;
			interrupt-parent = <&intc>;
			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
		};

		L2: cache-controller {
			compatible = "arm,l220-cache";
			reg = <0x1f002000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
			     <0 30 IRQ_TYPE_LEVEL_HIGH>,
			     <0 31 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-level = <2>;
			/*
			 * Override default cache size, sets and
			 * associativity as these may be erroneously set
			 * up by boot loader(s), probably for safety
			 * since th outer sync operation can cause the
			 * cache to hang unless disabled.
			 */
			cache-size = <1048576>; // 1MB
			cache-sets = <4096>;
			cache-line-size = <32>;
			arm,shared-override;
			arm,parity-enable;
			arm,outer-sync-disable;
		};

		scu: scu@1f000000 {
			compatible = "arm,arm11mp-scu";
			reg = <0x1f000000 0x100>;
		};

		twd_timer: timer@1f000600 {
			compatible = "arm,arm11mp-twd-timer";

Annotation

Implementation Notes