arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts
Extension
.dts
Size
4759 bytes
Lines
227
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A5x2
 * Cortex-A5 MPCore (V2P-CA5s)
 *
 * HBI-0225B
 */

/dts-v1/;
#include "vexpress-v2m-rs1.dtsi"

/ {
	model = "V2P-CA5s";
	arm,hbi = <0x225>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <1>;
			next-level-cache = <&L2>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* Chipselect 2 is physically at 0x18000000 */
		vram: vram@18000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0x18000000 0x00800000>;
			no-map;
		};
	};

Annotation

Implementation Notes