arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts- Extension
.dts- Size
- 5706 bytes
- Lines
- 275
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
aspeed-g5.dtsidt-bindings/gpio/aspeed-gpio.hdt-bindings/interrupt-controller/irq.hopenbmc-flash-layout-64.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/{
model = "ASRock ROMED8HM3 BMC v1.00";
compatible = "asrock,romed8hm3-bmc", "aspeed,ast2500";
aliases {
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
bootargs = "console=tty0 console=ttyS4,115200 earlycon";
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
leds {
compatible = "gpio-leds";
heartbeat {
gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
system-fault {
gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
panic-indicator;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
<&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-max-frequency = <50000000>; /* 50 MHz */
#include "openbmc-flash-layout-64.dtsi"
};
};
&uart5 {
status = "okay";
};
&vuart {
status = "okay";
aspeed,lpc-io-reg = <0x2f8>;
aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
};
&mac0 {
status = "okay";
Annotation
- Immediate include surface: `aspeed-g5.dtsi`, `dt-bindings/gpio/aspeed-gpio.h`, `dt-bindings/interrupt-controller/irq.h`, `openbmc-flash-layout-64.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.