arch/arm/boot/dts/aspeed/aspeed-g5.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/aspeed/aspeed-g5.dtsi
Extension
.dtsi
Size
33856 bytes
Lines
1639
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>

/ {
	model = "Aspeed BMC";
	compatible = "aspeed,ast2500";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&vic>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		i2c9 = &i2c9;
		i2c10 = &i2c10;
		i2c11 = &i2c11;
		i2c12 = &i2c12;
		i2c13 = &i2c13;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &vuart;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,arm1176jzf-s";
			device_type = "cpu";
			reg = <0>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		fmc: spi@1e620000 {
			reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "aspeed,ast2500-fmc";
			clocks = <&syscon ASPEED_CLK_AHB>;
			status = "disabled";
			interrupts = <19>;
			flash@0 {
				reg = < 0 >;
				compatible = "jedec,spi-nor";
				spi-max-frequency = <50000000>;
				spi-rx-bus-width = <2>;
				status = "disabled";

Annotation

Implementation Notes