arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi
Extension
.dtsi
Size
15715 bytes
Lines
627
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/bcm-cygnus.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "brcm,cygnus";
	model = "Broadcom Cygnus SoC";
	interrupt-parent = <&gic>;

	aliases {
		ethernet0 = &eth0;
	};

	memory@0 {
		device_type = "memory";
		reg = <0 0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
		};
	};

	/include/ "bcm-cygnus-clock.dtsi"

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	};

	core@19000000 {
		compatible = "simple-bus";
		ranges = <0x00000000 0x19000000 0x1000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		timer@20200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20200 0x100>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
			clocks = <&periph_clk>;
		};

		gic: interrupt-controller@21000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x21000 0x1000>,
			      <0x20100 0x100>;
		};

		L2: cache-controller@22000 {
			compatible = "arm,pl310-cache";
			reg = <0x22000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};
	};

	axi {

Annotation

Implementation Notes