arch/arm/boot/dts/broadcom/bcm2837.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/broadcom/bcm2837.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/broadcom/bcm2837.dtsi
Extension
.dtsi
Size
4046 bytes
Lines
145
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "bcm283x.dtsi"
#include "bcm2835-common.dtsi"

/ {
	compatible = "brcm,bcm2837";

	soc {
		ranges = <0x7e000000 0x3f000000 0x1000000>,
			 <0x40000000 0x40000000 0x00001000>;
		dma-ranges = <0xc0000000 0x00000000 0x3f000000>;

		local_intc: interrupt-controller@40000000 {
			compatible = "brcm,bcm2836-l1-intc";
			reg = <0x40000000 0x100>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&local_intc>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupt-parent = <&local_intc>;
		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&local_intc>;
		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
			     <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
			     <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
			     <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
		always-on;
	};

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit

		/* Source for d/i-cache-line-size and d/i-cache-sets
		 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
		 * /about-the-l1-memory-system?lang=en
		 *
		 * Source for d/i-cache-size
		 * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
		 */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x000000d8>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <1>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x000000e0>;
			d-cache-size = <0x8000>;

Annotation

Implementation Notes