arch/arm/boot/dts/broadcom/bcm63138.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/broadcom/bcm63138.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/broadcom/bcm63138.dtsi- Extension
.dtsi- Size
- 7663 bytes
- Lines
- 345
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.hdt-bindings/interrupt-controller/irq.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Broadcom BCM63138 DSL SoCs Device Tree
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm63138", "brcm,bcmbca";
model = "Broadcom BCM963138 Reference Board";
interrupt-parent = <&gic>;
aliases {
uart0 = &serial0;
uart1 = &serial1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0>;
enable-method = "brcm,bcm63138";
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <1>;
enable-method = "brcm,bcm63138";
resets = <&pmb0 4 1>;
};
};
clocks {
/* UBUS peripheral clock */
periph_clk: periph_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "periph";
};
/* peripheral clock for system timer */
axi_clk: axi_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&armpll>;
clock-div = <2>;
clock-mult = <1>;
};
/* APB bus clock */
apb_clk: apb_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&armpll>;
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/interrupt-controller/irq.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.