arch/arm/boot/dts/broadcom/bcm7445.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/broadcom/bcm7445.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/broadcom/bcm7445.dtsi- Extension
.dtsi- Size
- 7370 bytes
- Lines
- 319
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Broadcom STB (bcm7445)";
compatible = "brcm,bcm7445", "brcm,brcmstb";
interrupt-parent = <&gic>;
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "brcm,brahma-b15";
device_type = "cpu";
enable-method = "brcm,brahma-b15";
reg = <0>;
};
cpu@1 {
compatible = "brcm,brahma-b15";
device_type = "cpu";
enable-method = "brcm,brahma-b15";
reg = <1>;
};
cpu@2 {
compatible = "brcm,brahma-b15";
device_type = "cpu";
enable-method = "brcm,brahma-b15";
reg = <2>;
};
cpu@3 {
compatible = "brcm,brahma-b15";
device_type = "cpu";
enable-method = "brcm,brahma-b15";
reg = <3>;
};
};
gic: interrupt-controller@ffd00000 {
compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
reg = <0x00 0xffd01000 0x00 0x1000>,
<0x00 0xffd02000 0x00 0x2000>,
<0x00 0xffd04000 0x00 0x2000>,
<0x00 0xffd06000 0x00 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
};
rdb@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0 0x00 0xf0000000 0x1000000>;
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.