arch/arm/boot/dts/hisilicon/hi3620.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/hisilicon/hi3620.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/hisilicon/hi3620.dtsi
Extension
.dtsi
Size
15208 bytes
Lines
576
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * HiSilicon Ltd. Hi3620 SoC
 *
 * Copyright (C) 2012-2013 HiSilicon Ltd.
 * Copyright (C) 2012-2013 Linaro Ltd.
 *
 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
 */

#include <dt-bindings/clock/hi3620-clock.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
	};

	pclk: clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "apb_pclk";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "hisilicon,hi3620-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
		};
	};

	amba-bus {

		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";

Annotation

Implementation Notes