arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts
Extension
.dts
Size
5646 bytes
Lines
183
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Goramo MultiLink Router
 * There are two variants:
 * - MultiLink Basic (a box)
 * - MultiLink Max (19" rack mount)
 * This device tree supports MultiLink Basic.
 * This machine is based on IXP425.
 * This is one of the few devices supporting the IXP4xx High-Speed Serial
 * (HSS) link for a V.35 WAN interface.
 * The hardware originates in Poland.
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Goramo MultiLink Router";
	compatible = "goramo,multilink-router", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/*
		 * 64 MB of RAM according to the manual. The MultiLink
		 * Max has 128 MB.
		 */
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	/*
	 * 74HC4094 which is used as a rudimentary GPIO expander
	 * FIXME:
	 * - Create device tree bindings for this as GPIO expander
	 * - Write a pure DT GPIO driver using these bindings
	 * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different)
	 */
	gpio_74: gpio-74hc4094 {
		compatible = "nxp,74hc4094";
		cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
		d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
		str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
		/* oe-gpios is optional */
		gpio-controller;
		#gpio-cells = <2>;
		/* We are not cascaded */
		registers-number = <1>;
		gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N",
				"CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET",
				"CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N";
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;

Annotation

Implementation Notes