arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts- Extension
.dts- Size
- 1376 bytes
- Lines
- 69
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
intel-ixp43x.dtsiintel-ixp4xx-reference-design.dtsidt-bindings/input/input.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Intel KIXRP435 Control Plane
* processor reference design.
*/
/dts-v1/;
#include "intel-ixp43x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Intel KIXRP435 Reference Design";
compatible = "intel,kixrp435", "intel,ixp43x";
#address-cells = <1>;
#size-cells = <1>;
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
};
/* CHECKME: ethernet set-up taken from Gateworks Cambria */
ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
};
};
ethernet@c800c000 {
status = "okay";
queue-rx = <&qmgr 2>;
queue-txready = <&qmgr 19>;
phy-mode = "rgmii";
phy-handle = <&phy2>;
intel,npe-handle = <&npe 0>;
};
};
};
Annotation
- Immediate include surface: `intel-ixp43x.dtsi`, `intel-ixp4xx-reference-design.dtsi`, `dt-bindings/input/input.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.