arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi- Extension
.dtsi- Size
- 2139 bytes
- Lines
- 87
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
intel-ixp4xx.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: ISC
/*
* Device Tree file for Intel XScale Network Processors
* in the IXP45x and IXP46x series. This series has 64 interrupts and adds a
* few more peripherals over the 42x and 43x series so this extends the
* basic IXP4xx DTSI.
*/
#include "intel-ixp4xx.dtsi"
/ {
soc {
bus@c4000000 {
compatible = "intel,ixp46x-expansion-bus-controller", "syscon";
/* Uses at least up to 0x124 */
reg = <0xc4000000 0x1000>;
};
rng@70002100 {
compatible = "intel,ixp46x-rng";
reg = <0x70002100 4>;
};
interrupt-controller@c8003000 {
compatible = "intel,ixp43x-interrupt";
};
/*
* This is the USB Device Mode (UDC) controller, which is used
* to present the IXP4xx as a device on a USB bus.
*/
usb@c800b000 {
compatible = "intel,ixp4xx-udc";
reg = <0xc800b000 0x1000>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c@c8011000 {
compatible = "intel,ixp4xx-i2c";
reg = <0xc8011000 0x18>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
/* This is known as EthB1 */
ethernet@c800d000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc800d000 0x1000>;
status = "disabled";
intel,npe = <1>;
/* Dummy values that depend on firmware */
queue-rx = <&qmgr 0>;
queue-txready = <&qmgr 0>;
};
/* This is known as EthB2 */
ethernet@c800e000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc800e000 0x1000>;
status = "disabled";
intel,npe = <2>;
/* Dummy values that depend on firmware */
queue-rx = <&qmgr 0>;
queue-txready = <&qmgr 0>;
};
/* This is known as EthB3 */
ethernet@c800f000 {
compatible = "intel,ixp4xx-ethernet";
reg = <0xc800f000 0x1000>;
Annotation
- Immediate include surface: `intel-ixp4xx.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.