arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi- Extension
.dtsi- Size
- 5395 bytes
- Lines
- 203
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/irq.hdt-bindings/gpio/gpio.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: ISC
/*
* Device Tree file for Intel XScale Network Processors
* in the IXP 4xx series.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
interrupt-parent = <&intcon>;
/*
* The IXP4xx expansion bus is a set of up to 7 each up to 16MB
* windows in the 256MB space from 0x50000000 to 0x5fffffff.
*/
bus@c4000000 {
/* compatible and reg filled in by per-soc device tree */
native-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x01000000>,
<1 0x0 0x51000000 0x01000000>,
<2 0x0 0x52000000 0x01000000>,
<3 0x0 0x53000000 0x01000000>,
<4 0x0 0x54000000 0x01000000>,
<5 0x0 0x55000000 0x01000000>,
<6 0x0 0x56000000 0x01000000>,
<7 0x0 0x57000000 0x01000000>;
dma-ranges = <0 0x0 0x50000000 0x01000000>,
<1 0x0 0x51000000 0x01000000>,
<2 0x0 0x52000000 0x01000000>,
<3 0x0 0x53000000 0x01000000>,
<4 0x0 0x54000000 0x01000000>,
<5 0x0 0x55000000 0x01000000>,
<6 0x0 0x56000000 0x01000000>,
<7 0x0 0x57000000 0x01000000>;
};
qmgr: queue-manager@60000000 {
compatible = "intel,ixp4xx-ahb-queue-manager";
reg = <0x60000000 0x4000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
};
pci@c0000000 {
/* compatible filled in by per-soc device tree */
reg = <0xc0000000 0x1000>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
<9 IRQ_TYPE_LEVEL_HIGH>,
<10 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
status = "disabled";
ranges =
/*
* 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
* done in 4 chunks of 16MB each.
*/
<0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
/* 64KB I/O space at 0x4c000000 */
<0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/gpio/gpio.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.