arch/arm/boot/dts/intel/socfpga/Makefile

File Facts

System

Linux kernel

Corpus path

arch/arm/boot/dts/intel/socfpga/Makefile

Extension

[no extension]

Size

1632 bytes

Lines

42

Domain

Architecture Layer

Bucket

arch/arm

Inferred role

Architecture Layer: build/configuration rule

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
	socfpga_arria5_socdk.dtb \
	socfpga_arria10_chameleonv3.dtb \
	socfpga_arria10_mercury_aa1_pe1_emmc.dtb \
	socfpga_arria10_mercury_aa1_pe1_qspi.dtb \
	socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \
	socfpga_arria10_mercury_aa1_pe3_emmc.dtb \
	socfpga_arria10_mercury_aa1_pe3_qspi.dtb \
	socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \
	socfpga_arria10_mercury_aa1_st1_emmc.dtb \
	socfpga_arria10_mercury_aa1_st1_qspi.dtb \
	socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
	socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
	socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
	socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
	socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \
	socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \
	socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \
	socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \
	socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \
	socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \
	socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \
	socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \
	socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \
	socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \
	socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \
	socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \
	socfpga_arria10_socdk_nand.dtb \
	socfpga_arria10_socdk_qspi.dtb \
	socfpga_arria10_socdk_sdmmc.dtb \
	socfpga_cyclone5_chameleon96.dtb \
	socfpga_cyclone5_mcvevk.dtb \
	socfpga_cyclone5_socdk.dtb \
	socfpga_cyclone5_de0_nano_soc.dtb \
	socfpga_cyclone5_de10nano.dtb \
	socfpga_cyclone5_sockit.dtb \
	socfpga_cyclone5_socrates.dtb \
	socfpga_cyclone5_sodia.dtb \
	socfpga_cyclone5_vining_fpga.dtb \
	socfpga_vt.dtb

Annotation

• Atlas domain: Architecture Layer / arch/arm.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.