arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts- Extension
.dts- Size
- 1717 bytes
- Lines
- 102
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
socfpga_cyclone5.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright Altera Corporation (C) 2015. All rights reserved.
*/
#include "socfpga_cyclone5.dtsi"
/ {
model = "Terasic DE-0(Atlas)";
compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory@0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
aliases {
ethernet0 = &gmac1;
};
regulator_3_3v: regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
leds {
compatible = "gpio-leds";
led-hps0 {
label = "hps_led0";
gpios = <&portb 24 0>;
linux,default-trigger = "heartbeat";
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <1860>; /* 960ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
max-frame-size = <3800>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
Annotation
- Immediate include surface: `socfpga_cyclone5.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.