arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts
Extension
.dts
Size
1800 bytes
Lines
96
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017, Intel Corporation
 *
 * based on socfpga_cyclone5_de0_nano_soc.dts
 */
/dts-v1/;

#include "socfpga_cyclone5.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Terasic DE10-Nano";
	compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		/* 1 GiB */
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};

	soc {
		fpga: bus@ff200000 {
			compatible = "simple-bus";
			reg = <0xff200000 0x00200000>;
			ranges = <0x00000000 0xff200000 0x00200000>;
			#address-cells = <1>;
			#size-cells = <1>;

			/*
			 * Here the devices will appear if an FPGA image is
			 * loaded. Their description is expected to be added
			 * using a device tree overlay that matches the image.
			 */
		};
	};
};

&gmac1 {
	/* Uses a KSZ9031RNX phy */
	phy-mode = "rgmii-id";
	rxd0-skew-ps = <420>;
	rxd1-skew-ps = <420>;
	rxd2-skew-ps = <420>;
	rxd3-skew-ps = <420>;
	txen-skew-ps = <0>;
	rxdv-skew-ps = <420>;
	status = "okay";
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&i2c0 {
	clock-frequency = <100000>;
	status = "okay";

Annotation

Implementation Notes