arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcv.dtsi

File Facts

System

Linux kernel

Corpus path

arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcv.dtsi

Extension

.dtsi

Size

415 bytes

Lines

24

Domain

Architecture Layer

Bucket

arch/arm

Inferred role

Architecture Layer: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• socfpga_cyclone5.dtsi

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
 */

#include "socfpga_cyclone5.dtsi"

/ {
	model = "Aries/DENX MCV";
	compatible = "altr,socfpga-cyclone5", "altr,socfpga";

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1 GiB */
	};
};

&mmc0 {	/* On-SoM eMMC */
	bus-width = <8>;
	clk-phase-sd-hs = <0>, <135>;
	status = "okay";
};

Annotation

• Immediate include surface: `socfpga_cyclone5.dtsi`.
• Atlas domain: Architecture Layer / arch/arm.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.