arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts- Extension
.dts- Size
- 1200 bytes
- Lines
- 80
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
socfpga_cyclone5_mcv.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
*/
#include "socfpga_cyclone5_mcv.dtsi"
/ {
model = "Aries/DENX MCV EVK";
compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";
aliases {
ethernet0 = &gmac0;
stmpe-i2c0 = &stmpe1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
&gmac0 {
phy-mode = "rgmii";
status = "okay";
};
&gpio0 { /* GPIO 0 ... 28 */
status = "okay";
};
&gpio1 { /* GPIO 29 ... 57 */
status = "okay";
};
&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
stmpe1: stmpe811@41 {
compatible = "st,stmpe811";
reg = <0x41>;
id = <0>;
blocks = <0x5>;
irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */
stmpe_touchscreen {
compatible = "st,stmpe-ts";
ts,sample-time = <4>;
ts,mod-12b = <1>;
ts,ref-sel = <0>;
ts,adc-freq = <1>;
ts,ave-ctrl = <1>;
ts,touch-det-delay = <3>;
ts,settling = <4>;
ts,fraction-z = <7>;
ts,i-drive = <1>;
};
};
Annotation
- Immediate include surface: `socfpga_cyclone5_mcv.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.