arch/arm/boot/dts/marvell/armada-370.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/marvell/armada-370.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/marvell/armada-370.dtsi
Extension
.dtsi
Size
10033 bytes
Lines
440
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 370 family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * Contains definitions specific to the Armada 370 SoC that are not
 * common to all Armada SoCs.
 */

#include "armada-370-xp.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	model = "Marvell Armada 370 family SoC";
	compatible = "marvell,armada370", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	soc {
		compatible = "marvell,armada370-mbus", "simple-bus";

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
		};

		pciec: pcie@82000000 {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
				0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;

			pcie0: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 58>;
				#interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie0_intc 0>,

Annotation

Implementation Notes