arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi
Extension
.dtsi
Size
10534 bytes
Lines
493
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
 *
 *  Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
 */

/*
	SERDES mapping -
	0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
	1. 6141 switch (2.5Gbps capable)
	2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
	3. USB 3.0 Host
	4. mini PCIe CON2 - PCIe2
	5. SFP connector, or optionally SGMII Ethernet 1512 PHY

	USB 2.0 mapping -
	0. USB 2.0 - 0 USB pins header CON12
	1. USB 2.0 - 1 mini PCIe CON2
	2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)

	Pin mapping -
	0,1 - console UART
	2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
	      front panel and PSE controller
	4,5 - MDC/MDIO
	6..17 - RGMII
	18 - Topaz switch reset (active low)
	19 - 1512 phy reset
	20 - 1512 phy reset (eth2, optional)
	21,28,37,38,39,40 - SD0
	22 - USB 3.0 current limiter enable (active high)
	24 - SFP TX fault (input active high)
	25 - SFP present (input active low)
	26,27 - I2C1 - connected to SFP
	29 - Fan PWM
	30 - CON4 mini PCIe wifi disable
	31 - CON3 mini PCIe wifi disable
	32 - Fuse programming power toggle (1.8v)
	33 - CON4 mini PCIe reset
	34 - CON2 mini PCIe wifi disable
	35 - CON3 mini PCIe reset
	36 - Rear button (GPIO active low)
	41 - CON1 front panel connector
	42 - Front LED1, or front panel CON1
	43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
	44 - CON2 mini PCIe reset
	45 - TPM PIRQ signal, or front panel CON1
	46 - SFP TX disable
	47 - Control isolation of boot sensitive SAR signals
	48 - PSE reset
	49 - PSE OSS signal
	50 - PSE interrupt
	52 - Front LED2, or front panel
	53 - Front button
	54 - SFP LOS (input active high)
	55 - Fan sense
	56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
	59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
*/

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "armada-385.dtsi"

/ {
	compatible = "marvell,armada385", "marvell,armada380";

Annotation

Implementation Notes