arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi- Extension
.dtsi- Size
- 13223 bytes
- Lines
- 454
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
armada-xp.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* Contains definitions specific to the Armada XP MV78460 SoC that are not
* common to all Armada XP SoCs.
*/
#include "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78460 SoC";
compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,armada-xp-smp";
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
clock-latency = <1000000>;
};
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
clock-latency = <1000000>;
};
cpu@2 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <2>;
clocks = <&cpuclk 2>;
clock-latency = <1000000>;
};
cpu@3 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <3>;
clocks = <&cpuclk 3>;
clock-latency = <1000000>;
};
};
soc {
/*
* MV78460 has 4 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
pciec: pcie@82000000 {
Annotation
- Immediate include surface: `armada-xp.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.