arch/arm/boot/dts/marvell/kirkwood-6282.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/marvell/kirkwood-6282.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/marvell/kirkwood-6282.dtsi
Extension
.dtsi
Size
4246 bytes
Lines
162
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/ {
	mbus@f1000000 {
		pciec: pcie@82000000 {
			compatible = "marvell,kirkwood-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
			        0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0       1 0 /* Port 1.0 MEM */
				0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0       1 0 /* Port 1.0 IO  */>;

			pcie0: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-names = "intx", "error";
				interrupts = <9>, <44>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie0_intc 0>,
						<0 0 0 2 &pcie0_intc 1>,
						<0 0 0 3 &pcie0_intc 2>,
						<0 0 0 4 &pcie0_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gate_clk 2>;
				status = "disabled";

				pcie0_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie1: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-names = "intx", "error";
				interrupts = <10>, <45>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
						<0 0 0 2 &pcie1_intc 1>,
						<0 0 0 3 &pcie1_intc 2>,
						<0 0 0 4 &pcie1_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gate_clk 18>;

Annotation

Implementation Notes