arch/arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts- Extension
.dts- Size
- 595 bytes
- Lines
- 35
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
kirkwood-rd88f6281.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Marvell RD88F6181 Z0 stepping descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
* This file contains the definitions for the board using the Z0
* stepping of the SoC. The ethernet switch has a "wan" port.
*/
/dts-v1/;
#include "kirkwood-rd88f6281.dtsi"
/ {
model = "Marvell RD88f6281 Reference design, with Z0 SoC";
compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
};
ð1 {
status = "disabled";
};
&switch {
reg = <0>;
ports {
port@4 {
reg = <4>;
label = "wan";
};
};
};
Annotation
- Immediate include surface: `kirkwood-rd88f6281.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.