arch/arm/boot/dts/mediatek/mt7623n.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/mediatek/mt7623n.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/mediatek/mt7623n.dtsi
Extension
.dtsi
Size
8333 bytes
Lines
302
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright © 2017-2020 MediaTek Inc.
 * Author: Sean Wang <sean.wang@mediatek.com>
 *	   Ryder Lee <ryder.lee@mediatek.com>
 *
 */

#include "mt7623.dtsi"
#include <dt-bindings/memory/mt2701-larb-port.h>

/ {
	aliases {
		rdma0 = &rdma0;
		rdma1 = &rdma1;
	};

	g3dsys: syscon@13000000 {
		compatible = "mediatek,mt7623-g3dsys",
			     "mediatek,mt2701-g3dsys",
			     "syscon";
		reg = <0 0x13000000 0 0x200>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	mali: gpu@13040000 {
		compatible = "mediatek,mt7623-mali", "arm,mali-450";
		reg = <0 0x13040000 0 0x30000>;
		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
				  "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
				  "pp";
		clocks = <&topckgen CLK_TOP_MMPLL>,
			 <&g3dsys CLK_G3DSYS_CORE>;
		clock-names = "bus", "core";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
		resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
	};

	mmsys: syscon@14000000 {
		compatible = "mediatek,mt7623-mmsys",
			     "mediatek,mt2701-mmsys",
			     "syscon";
		reg = <0 0x14000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb0: larb@14010000 {
		compatible = "mediatek,mt7623-smi-larb",
			     "mediatek,mt2701-smi-larb";
		reg = <0 0x14010000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		mediatek,larb-id = <0>;
		clocks = <&mmsys CLK_MM_SMI_LARB0>,
			 <&mmsys CLK_MM_SMI_LARB0>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

Annotation

Implementation Notes