arch/arm/boot/dts/microchip/at91-linea.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/microchip/at91-linea.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/microchip/at91-linea.dtsi
Extension
.dtsi
Size
1104 bytes
Lines
72
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module.
 *
 * Copyright (C) 2017 Axentia Technologies AB
 *
 * Author: Peter Rosin <peda@axentia.se>
 */

#include "sama5d31.dtsi"

/ {
	compatible = "axentia,linea",
		     "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";

	memory@20000000 {
		reg = <0x20000000 0x4000000>;
	};
};

&slow_xtal {
	clock-frequency = <32768>;
};

&main_xtal {
	clock-frequency = <12000000>;
};

&tcb0 {
	timer@0 {
		compatible = "atmel,tcb-timer";
		reg = <0>;
	};

	timer@1 {
		compatible = "atmel,tcb-timer";
		reg = <1>;
	};
};

&i2c0 {
	status = "okay";

	eeprom@51 {
		compatible = "st,24c64", "atmel,24c64";
		reg = <0x51>;
		pagesize = <32>;
	};
};

&ebi {
	pinctrl-0 = <&pinctrl_ebi_nand_addr>;
	pinctrl-names = "default";
	status = "okay";
};


&nand_controller {
	status = "okay";

	nand: nand@3 {
		reg = <0x3 0x0 0x2>;
		atmel,rb = <0>;
		nand-bus-width = <8>;
		nand-ecc-mode = "hw";
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;
		nand-on-flash-bbt;
		label = "atmel_nand";
	};

Annotation

Implementation Notes