arch/arm/boot/dts/microchip/at91sam9g20ek.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/microchip/at91sam9g20ek.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/microchip/at91sam9g20ek.dts- Extension
.dts- Size
- 593 bytes
- Lines
- 29
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
at91sam9g20ek_common.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*/
/dts-v1/;
#include "at91sam9g20ek_common.dtsi"
/ {
model = "Atmel at91sam9g20ek";
compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
leds {
compatible = "gpio-leds";
led-ds1 {
label = "ds1";
gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-ds5 {
label = "ds5";
gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
};
};
};
Annotation
- Immediate include surface: `at91sam9g20ek_common.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.