arch/arm/boot/dts/microchip/pm9g45.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/microchip/pm9g45.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/microchip/pm9g45.dts- Extension
.dts- Size
- 3354 bytes
- Lines
- 186
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
at91sam9g45.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* pm9g45.dts - Device Tree file for Ronetix pm9g45 board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*/
/dts-v1/;
#include "at91sam9g45.dtsi"
/ {
model = "Ronetix pm9g45";
compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9";
chosen {
bootargs = "console=ttyS0,115200";
};
memory@70000000 {
reg = <0x70000000 0x8000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
dbgu: serial@ffffee00 {
status = "okay";
};
pinctrl@fffff200 {
nand {
pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
<AT91_PIOD 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
mmc {
pinctrl_board_mmc: mmc0-board {
atmel,pins =
<AT91_PIOD 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD6 gpio CD pin pull_up and deglitch */
};
};
};
tcb0: timer@fff7c000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
mmc0: mmc@fff80000 {
pinctrl-0 = <
&pinctrl_board_mmc
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
Annotation
- Immediate include surface: `at91sam9g45.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.