arch/arm/boot/dts/microchip/sama5d2.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/microchip/sama5d2.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/microchip/sama5d2.dtsi- Extension
.dtsi- Size
- 33152 bytes
- Lines
- 1170
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/dma/at91.hdt-bindings/interrupt-controller/irq.hdt-bindings/clock/at91.hdt-bindings/mfd/at91-usart.hdt-bindings/iio/adc/at91-sama5d2_adc.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
*
* Copyright (C) 2015 Atmel,
* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
*/
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Atmel SAMA5D2 family SoC";
compatible = "atmel,sama5d2";
interrupt-parent = <&aic>;
aliases {
serial0 = &uart1;
serial1 = &uart3;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0>;
d-cache-size = <0x8000>; // L1, 32 KB
i-cache-size = <0x8000>; // L1, 32 KB
next-level-cache = <&L2>;
};
};
pmu {
compatible = "arm,cortex-a5-pmu";
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
};
etb@740000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x740000 0x1000>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "apb_pclk";
in-ports {
port {
etb_in: endpoint {
remote-endpoint = <&etm_out>;
};
};
};
};
etm@73c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x73c000 0x1000>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "apb_pclk";
out-ports {
port {
Annotation
- Immediate include surface: `dt-bindings/dma/at91.h`, `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/clock/at91.h`, `dt-bindings/mfd/at91-usart.h`, `dt-bindings/iio/adc/at91-sama5d2_adc.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.