arch/arm/boot/dts/microchip/sama7d65-pinfunc.h
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/microchip/sama7d65-pinfunc.h
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/microchip/sama7d65-pinfunc.h- Extension
.h- Size
- 39203 bytes
- Lines
- 948
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#define PINMUX_PIN(no, func, ioset) \
(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20))
#define PIN_PA0 0
#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0)
#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1)
#define PIN_PA0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA0, 2, 1)
#define PIN_PA0__NWER0 PINMUX_PIN(PIN_PA0, 3, 1)
#define PIN_PA1 1
#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0)
#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1)
#define PIN_PA1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA1, 2, 1)
#define PIN_PA1__A21 PINMUX_PIN(PIN_PA1, 3, 1)
#define PIN_PA2 2
#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0)
#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1)
#define PIN_PA2__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA2, 2, 1)
#define PIN_PA2__A22 PINMUX_PIN(PIN_PA2, 3, 1)
#define PIN_PA3 3
#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0)
#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1)
#define PIN_PA3__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA3, 2, 1)
#define PIN_PA3__D0 PINMUX_PIN(PIN_PA3, 3, 1)
#define PIN_PA4 4
#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0)
#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1)
#define PIN_PA4__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA4, 2, 1)
#define PIN_PA4__D1 PINMUX_PIN(PIN_PA4, 3, 1)
#define PIN_PA5 5
#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0)
#define PIN_PA5__SDMMC0_DAT4 PINMUX_PIN(PIN_PA5, 1, 1)
#define PIN_PA5__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA5, 2, 3)
#define PIN_PA5__D4 PINMUX_PIN(PIN_PA5, 3, 1)
#define PIN_PA5__TCLK4 PINMUX_PIN(PIN_PA5, 6, 3)
#define PIN_PA6 6
#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0)
#define PIN_PA6__SDMMC0_DAT5 PINMUX_PIN(PIN_PA6, 1, 1)
#define PIN_PA6__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA6, 2, 3)
#define PIN_PA6__D5 PINMUX_PIN(PIN_PA6, 3, 1)
#define PIN_PA6__TIOB4 PINMUX_PIN(PIN_PA6, 6, 3)
#define PIN_PA7 7
#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0)
#define PIN_PA7__SDMMC0_DAT6 PINMUX_PIN(PIN_PA7, 1, 1)
#define PIN_PA7__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA7, 2, 3)
#define PIN_PA7__D6 PINMUX_PIN(PIN_PA7, 3, 1)
#define PIN_PA7__TIOA4 PINMUX_PIN(PIN_PA7, 6, 3)
#define PIN_PA8 8
#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0)
#define PIN_PA8__SDMMC0_DAT7 PINMUX_PIN(PIN_PA8, 1, 1)
#define PIN_PA8__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA8, 2, 3)
#define PIN_PA8__D7 PINMUX_PIN(PIN_PA8, 3, 1)
#define PIN_PA8__TIOA5 PINMUX_PIN(PIN_PA8, 6, 3)
#define PIN_PA9 9
#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0)
#define PIN_PA9__SDMMC0_DAT2 PINMUX_PIN(PIN_PA9, 1, 1)
#define PIN_PA9__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA9, 2, 1)
#define PIN_PA9__D2 PINMUX_PIN(PIN_PA9, 3, 1)
#define PIN_PA9__TIOB5 PINMUX_PIN(PIN_PA9, 6, 3)
#define PIN_PA10 10
#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0)
#define PIN_PA10__SDMMC0_DAT3 PINMUX_PIN(PIN_PA10, 1, 1)
#define PIN_PA10__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA10, 2, 1)
#define PIN_PA10__D3 PINMUX_PIN(PIN_PA10, 3, 1)
#define PIN_PA10__TCLK5 PINMUX_PIN(PIN_PA10, 6, 3)
#define PIN_PA11 11
#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0)
#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1)
#define PIN_PA11__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA11, 2, 1)
#define PIN_PA11__NANDRDY PINMUX_PIN(PIN_PA11, 3, 1)
#define PIN_PA11__TIOB3 PINMUX_PIN(PIN_PA11, 6, 3)
#define PIN_PA12 12
#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0)
#define PIN_PA12__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA12, 2, 1)
#define PIN_PA12__NRD PINMUX_PIN(PIN_PA12, 3, 1)
#define PIN_PA12__PCK0 PINMUX_PIN(PIN_PA12, 4, 1)
#define PIN_PA12__EXT_IRQ0 PINMUX_PIN(PIN_PA12, 5, 1)
#define PIN_PA12__TIOA3 PINMUX_PIN(PIN_PA12, 6, 3)
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.