arch/arm/boot/dts/microchip/sama7g5.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/microchip/sama7g5.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/microchip/sama7g5.dtsi
Extension
.dtsi
Size
30681 bytes
Lines
1054
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 *  sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
 *
 *  Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries
 *
 *  Author: Eugen Hristev <eugen.hristev@microchip.com>
 *  Author: Claudiu Beznea <claudiu.beznea@microchip.com>
 *
 */

#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	model = "Microchip SAMA7G5 family SoC";
	compatible = "microchip,sama7g5";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>; /* min followed by max */
			d-cache-size = <0x8000>;	// L1, 32 KB
			i-cache-size = <0x8000>;	// L1, 32 KB
			next-level-cache = <&L2>;

			L2: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-size = <0x40000>; // L2, 256 KB
				cache-unified;
			};
		};
	};

	cpu_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-90000000 {
			opp-hz = /bits/ 64 <90000000>;
			opp-microvolt = <1050000 1050000 1225000>;
			clock-latency-ns = <320000>;
		};

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <1050000 1050000 1225000>;
			clock-latency-ns = <320000>;
		};

		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;

Annotation

Implementation Notes