arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi- Extension
.dtsi- Size
- 58265 bytes
- Lines
- 2080
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
tegra124.dtsitegra124-apalis-emc.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2016-2018 Toradex AG
*/
#include "tegra124.dtsi"
#include "tegra124-apalis-emc.dtsi"
/*
* Toradex Apalis TK1 Module Device Tree
* Compatible for Revisions 2GB: V1.2A
*/
/ {
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
};
pcie@1003000 {
status = "okay";
avddio-pex-supply = <®_1v05_vdd>;
avdd-pex-pll-supply = <®_1v05_vdd>;
avdd-pll-erefe-supply = <®_1v05_avdd>;
dvddio-pex-supply = <®_1v05_vdd>;
hvdd-pex-pll-e-supply = <®_module_3v3>;
hvdd-pex-supply = <®_module_3v3>;
vddio-pex-ctl-supply = <®_module_3v3>;
/* Apalis PCIe (additional lane Apalis type specific) */
pci@1,0 {
/* PCIE1_RX/TX and TS_DIFF1/2 */
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
phy-names = "pcie-0", "pcie-1";
};
/* I210 Gigabit Ethernet Controller (On-module) */
pci@2,0 {
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
phy-names = "pcie-0";
status = "okay";
ethernet@0,0 {
reg = <0 0 0 0 0>;
local-mac-address = [00 00 00 00 00 00];
};
};
};
host1x@50000000 {
hdmi@54280000 {
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio =
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
pll-supply = <®_1v05_avdd_hdmi_pll>;
vdd-supply = <®_3v3_avdd_hdmi>;
};
};
gpu@57000000 {
/*
* Node left disabled on purpose - the bootloader will enable
* it after having set the VPR up
*/
vdd-supply = <®_vdd_gpu>;
};
gpio@6000d000 {
/* I210 Gigabit Ethernet Controller Reset */
lan-reset-n-hog {
Annotation
- Immediate include surface: `tegra124.dtsi`, `tegra124-apalis-emc.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.