arch/arm/boot/dts/nvidia/tegra20.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nvidia/tegra20.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nvidia/tegra20.dtsi
Extension
.dtsi
Size
29735 bytes
Lines
1078
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra20-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/tegra-pmc.h>

#include "tegra20-peripherals-opp.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&lic>;
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		device_type = "memory";
		reg = <0 0>;
	};

	sram@40000000 {
		compatible = "mmio-sram";
		reg = <0x40000000 0x40000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x40000000 0x40000>;

		vde_pool: sram@400 {
			reg = <0x400 0x3fc00>;
			pool;
		};
	};

	host1x@50000000 {
		compatible = "nvidia,tegra20-host1x";
		reg = <0x50000000 0x00024000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
		interrupt-names = "syncpt", "host1x";
		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
		clock-names = "host1x";
		resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
		reset-names = "host1x", "mc";
		power-domains = <&pd_core>;
		operating-points-v2 = <&host1x_dvfs_opp_table>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe@54040000 {
			compatible = "nvidia,tegra20-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_MPE>;
			resets = <&tegra_car 60>;
			reset-names = "mpe";
			power-domains = <&pd_mpe>;
			operating-points-v2 = <&mpe_dvfs_opp_table>;
			status = "disabled";
		};

		vi@54080000 {
			compatible = "nvidia,tegra20-vi";
			reg = <0x54080000 0x00000800>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_VI>;
			resets = <&tegra_car 20>;

Annotation

Implementation Notes