arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts- Extension
.dts- Size
- 2863 bytes
- Lines
- 133
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
tegra20-tamonten.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra20-tamonten.dtsi"
/ {
model = "Avionic Design Medcom-Wide board";
compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
aliases {
serial0 = &uartd;
};
chosen {
stdout-path = "serial0:115200n8";
};
host1x@50000000 {
dc@54200000 {
rgb {
status = "okay";
nvidia,panel = <&panel>;
};
};
};
pwm@7000a000 {
status = "okay";
};
i2c@7000c000 {
wm8903: wm8903@1a {
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
micdet-cfg = <0>;
micdet-delay = <100>;
gpio-cfg = <0xffffffff
0xffffffff
0
0xffffffff
0xffffffff>;
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
/* close enough */
power-supply = <&vdd_3v3_reg>;
};
panel: panel {
compatible = "innolux,n156bge-l21";
power-supply = <&vdd_1v8_reg>; // <&vdd_3v3_reg>;
enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
};
Annotation
- Immediate include surface: `tegra20-tamonten.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.