arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper.dtsi
Extension
.dtsi
Size
4109 bytes
Lines
149
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0

#include "tegra30-asus-nexus7-grouper-common.dtsi"
#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"

/ {
	compatible = "asus,grouper", "nvidia,tegra30";

	pinmux@70000868 {
		state_default: pinmux {
			lcd_dc1_pd2 {
				nvidia,pins = "lcd_dc1_pd2";
				nvidia,function = "displaya";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			lcd_pwr2_pc6 {
				nvidia,pins = "lcd_pwr2_pc6";
				nvidia,function = "displaya";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			spi2_cs2_n_pw3 {
				nvidia,pins = "spi2_cs2_n_pw3";
				nvidia,function = "spi2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			spi1_sck_px5 {
				nvidia,pins = "spi1_sck_px5";
				nvidia,function = "spi1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			pu5 {
				nvidia,pins = "pu5";
				nvidia,function = "pwm2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			spi1_miso_px7 {
				nvidia,pins = "spi1_miso_px7";
				nvidia,function = "spi1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			spi2_mosi_px0 {
				nvidia,pins = "spi2_mosi_px0";
				nvidia,function = "spi2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			kb_row7_pr7 {
				nvidia,pins = "kb_row7_pr7";
				nvidia,function = "kbc";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			pu3 {
				nvidia,pins = "pu3";
				nvidia,function = "rsvd4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Annotation

Implementation Notes