arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi- Extension
.dtsi- Size
- 17603 bytes
- Lines
- 715
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/input/input.hdt-bindings/thermal/thermal.htegra30.dtsitegra30-cpu-opp.dtsitegra30-cpu-opp-microvolt.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
#include "tegra30.dtsi"
#include "tegra30-cpu-opp.dtsi"
#include "tegra30-cpu-opp-microvolt.dtsi"
/**
* This file contains common DT entry for all fab version of Cardhu.
* There is multiple fab version of Cardhu starting from A01 to A07.
* Cardhu fab version A01 and A03 are not supported. Cardhu fab version
* A02 will have different sets of GPIOs for fixed regulator compare to
* Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
* compatible with fab version A04. Based on Cardhu fab version, the
* related dts file need to be chosen like for Cardhu fab version A02,
* use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
* tegra30-cardhu-a04.dts.
* The identification of board is done in two ways, by looking the sticker
* on PCB and by reading board id eeprom.
* The sticker will have number like 600-81291-1000-002 C.3. In this 4th
* number is the fab version like here it is 002 and hence fab version A02.
* The (downstream internal) U-Boot of Cardhu display the board-id as
* follows:
* BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
* In this Fab version is 02 i.e. A02.
* The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
* The location 0x8 of this eeprom contains the Fab version. It is 1 byte
* wide.
*/
/ {
model = "NVIDIA Tegra30 Cardhu evaluation board";
compatible = "nvidia,cardhu", "nvidia,tegra30";
aliases {
rtc0 = "/i2c@7000d000/tps65911@2d";
rtc1 = "/rtc@7000e000";
serial0 = &uarta;
serial1 = &uartc;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
pcie@3000 {
status = "okay";
/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
avdd-pexb-supply = <&ldo1_reg>;
vdd-pexb-supply = <&ldo1_reg>;
avdd-pex-pll-supply = <&ldo1_reg>;
hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
vddio-pex-ctl-supply = <&sys_3v3_reg>;
avdd-plle-supply = <&ldo2_reg>;
pci@1,0 {
nvidia,num-lanes = <4>;
};
pci@2,0 {
nvidia,num-lanes = <1>;
};
pci@3,0 {
status = "okay";
Annotation
- Immediate include surface: `dt-bindings/input/input.h`, `dt-bindings/thermal/thermal.h`, `tegra30.dtsi`, `tegra30-cpu-opp.dtsi`, `tegra30-cpu-opp-microvolt.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.