arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts- Extension
.dts- Size
- 18434 bytes
- Lines
- 576
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
tegra30-lg-x3.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-lg-x3.dtsi"
/ {
model = "LG Optimus Vu P895";
compatible = "lg,p895", "nvidia,tegra30";
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
/* GNSS UART-B pinmux */
uartb-cts-rxd {
nvidia,pins = "uart2_cts_n_pj5",
"uart2_rxd_pc3";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
uartb-rts-txd {
nvidia,pins = "uart2_rts_n_pj6",
"uart2_txd_pc2";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
gps-reset {
nvidia,pins = "spdif_out_pk5";
nvidia,function = "spdif";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
memo-key {
nvidia,pins = "sdmmc3_dat1_pb6";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
volume-up {
nvidia,pins = "gmi_cs7_n_pi6";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Sensors pinmux */
current-alert-irq {
nvidia,pins = "spi1_cs0_n_px6";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Panel pinmux */
panel-vdd {
nvidia,pins = "pbb0";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
Annotation
- Immediate include surface: `tegra30-lg-x3.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.