arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h

File Facts

System: Linux kernel
Corpus path: arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h
Extension: .h
Size: 12449 bytes
Lines: 297
Domain: Architecture Layer
Bucket: arch/arm
Inferred role: Architecture Layer: implementation source
Status: source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __DTS_IMX1_PINFUNC_H
#define __DTS_IMX1_PINFUNC_H

/*
 * The pin function ID is a tuple of
 * <pin mux_id>
 * mux_id consists of
 * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
 *
 * function:      0 - Primary function
 *                1 - Alternate function
 *                2 - GPIO
 * direction:     0 - Input
 *                1 - Output
 * gpio_oconf:    0 - A_IN
 *                1 - B_IN
 *                2 - A_OUT
 *                3 - Data Register
 * gpio_iconfa/b: 0 - GPIO_IN
 *                1 - Interrupt Status Register
 *                2 - 0
 *                3 - 1
 *
 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32
 * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is
 * the pin number on the specific port (between 0 and 31).
 */

#define MX1_PAD_A24__A24			0x00 0x004
#define MX1_PAD_A24__GPIO1_0			0x00 0x032
#define MX1_PAD_A24__SPI2_CLK			0x00 0x006
#define MX1_PAD_TIN__TIN			0x01 0x000
#define MX1_PAD_TIN__GPIO1_1			0x01 0x032
#define MX1_PAD_TIN__SPI2_RXD			0x01 0x022
#define MX1_PAD_PWMO__PWMO			0x02 0x004
#define MX1_PAD_PWMO__GPIO1_2			0x02 0x032
#define MX1_PAD_CSI_MCLK__CSI_MCLK		0x03 0x004
#define MX1_PAD_CSI_MCLK__GPIO1_3		0x03 0x032
#define MX1_PAD_CSI_D0__CSI_D0			0x04 0x000
#define MX1_PAD_CSI_D0__GPIO1_4			0x04 0x032
#define MX1_PAD_CSI_D1__CSI_D1			0x05 0x000
#define MX1_PAD_CSI_D1__GPIO1_5			0x05 0x032
#define MX1_PAD_CSI_D2__CSI_D2			0x06 0x000
#define MX1_PAD_CSI_D2__GPIO1_6			0x06 0x032
#define MX1_PAD_CSI_D3__CSI_D3			0x07 0x000
#define MX1_PAD_CSI_D3__GPIO1_7			0x07 0x032
#define MX1_PAD_CSI_D4__CSI_D4			0x08 0x000
#define MX1_PAD_CSI_D4__GPIO1_8			0x08 0x032
#define MX1_PAD_CSI_D5__CSI_D5			0x09 0x000
#define MX1_PAD_CSI_D5__GPIO1_9			0x09 0x032
#define MX1_PAD_CSI_D6__CSI_D6			0x0a 0x000
#define MX1_PAD_CSI_D6__GPIO1_10		0x0a 0x032
#define MX1_PAD_CSI_D7__CSI_D7			0x0b 0x000
#define MX1_PAD_CSI_D7__GPIO1_11		0x0b 0x032
#define MX1_PAD_CSI_VSYNC__CSI_VSYNC		0x0c 0x000
#define MX1_PAD_CSI_VSYNC__GPIO1_12		0x0c 0x032
#define MX1_PAD_CSI_HSYNC__CSI_HSYNC		0x0d 0x000
#define MX1_PAD_CSI_HSYNC__GPIO1_13		0x0d 0x032
#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK		0x0e 0x000
#define MX1_PAD_CSI_PIXCLK__GPIO1_14		0x0e 0x032
#define MX1_PAD_I2C_SDA__I2C_SDA		0x0f 0x000
#define MX1_PAD_I2C_SDA__GPIO1_15		0x0f 0x032
#define MX1_PAD_I2C_SCL__I2C_SCL		0x10 0x004
#define MX1_PAD_I2C_SCL__GPIO1_16		0x10 0x032
#define MX1_PAD_DTACK__DTACK			0x11 0x000
#define MX1_PAD_DTACK__GPIO1_17			0x11 0x032
#define MX1_PAD_DTACK__SPI2_SS			0x11 0x002
#define MX1_PAD_DTACK__A25			0x11 0x016
#define MX1_PAD_BCLK__BCLK			0x12 0x004
#define MX1_PAD_BCLK__GPIO1_18			0x12 0x032
#define MX1_PAD_LBA__LBA			0x13 0x004
#define MX1_PAD_LBA__GPIO1_19			0x13 0x032
#define MX1_PAD_ECB__ECB			0x14 0x000
#define MX1_PAD_ECB__GPIO1_20			0x14 0x032
#define MX1_PAD_A0__A0				0x15 0x004
#define MX1_PAD_A0__GPIO1_21			0x15 0x032
#define MX1_PAD_CS4__CS4			0x16 0x004
#define MX1_PAD_CS4__GPIO1_22			0x16 0x032
#define MX1_PAD_CS5__CS5			0x17 0x004
#define MX1_PAD_CS5__GPIO1_23			0x17 0x032
#define MX1_PAD_A16__A16			0x18 0x004
#define MX1_PAD_A16__GPIO1_24			0x18 0x032
#define MX1_PAD_A17__A17			0x19 0x004
#define MX1_PAD_A17__GPIO1_25			0x19 0x032
#define MX1_PAD_A18__A18			0x1a 0x004
#define MX1_PAD_A18__GPIO1_26			0x1a 0x032
#define MX1_PAD_A19__A19			0x1b 0x004
#define MX1_PAD_A19__GPIO1_27			0x1b 0x032
#define MX1_PAD_A20__A20			0x1c 0x004
#define MX1_PAD_A20__GPIO1_28			0x1c 0x032

Annotation

Atlas domain: Architecture Layer / arch/arm.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.