arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts- Extension
.dts- Size
- 2372 bytes
- Lines
- 102
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
imx25.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Sascha Hauer, Pengutronix
*/
/dts-v1/;
#include "imx25.dtsi"
/ {
model = "Ka-Ro TX25";
compatible = "karo,imx25-tx25", "fsl,imx25";
chosen {
stdout-path = &uart1;
};
reg_fec_phy: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "fec-phy";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 9 0>;
enable-active-high;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
};
};
&iomuxc {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX25_PAD_UART1_TXD__UART1_TXD 0x00000020
MX25_PAD_UART1_RXD__UART1_RXD 0x000000a0
MX25_PAD_UART1_CTS__UART1_CTS 0x00000060
MX25_PAD_UART1_RTS__UART1_RTS 0x000000e0
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX25_PAD_D11__GPIO_4_9 0x00000021 /* FEC PHY power on pin */
MX25_PAD_D13__GPIO_4_7 0x000000a1 /* FEC reset */
MX25_PAD_FEC_MDC__FEC_MDC 0x00000060
MX25_PAD_FEC_MDIO__FEC_MDIO 0x000001f0
MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x00000060
MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x00000060
MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x00000060
MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x000000c1
MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x000000c0
MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x000000c0
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x000000c0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX25_PAD_NF_CE0__NF_CE0 0x00000001
MX25_PAD_NFWE_B__NFWE_B 0x80000000
MX25_PAD_NFRE_B__NFRE_B 0x80000000
MX25_PAD_NFALE__NFALE 0x80000000
MX25_PAD_NFCLE__NFCLE 0x80000000
MX25_PAD_NFWP_B__NFWP_B 0x80000000
MX25_PAD_NFRB__NFRB 0x000000e0
MX25_PAD_D7__D7 0x00000080
MX25_PAD_D6__D6 0x00000080
MX25_PAD_D5__D5 0x00000080
MX25_PAD_D4__D4 0x00000080
Annotation
- Immediate include surface: `imx25.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.