arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h

File Facts

System: Linux kernel
Corpus path: arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h
Extension: .h
Size: 31904 bytes
Lines: 653
Domain: Architecture Layer
Bucket: arch/arm
Inferred role: Architecture Layer: implementation source
Status: source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __DTS_IMX25_PINFUNC_H
#define __DTS_IMX25_PINFUNC_H

/*
 * The pin function ID is a tuple of
 * <mux_reg conf_reg input_reg mux_mode input_val>
 */

#define MX25_PAD_A10__A10			0x008 0x000 0x000 0x00 0x000
#define MX25_PAD_A10__GPIO_4_0			0x008 0x000 0x000 0x05 0x000

#define MX25_PAD_A13__A13			0x00c 0x22C 0x000 0x00 0x000
#define MX25_PAD_A13__GPIO_4_1			0x00c 0x22C 0x000 0x05 0x000
#define MX25_PAD_A13__LCDC_CLS			0x00c 0x22C 0x000 0x07 0x000

#define MX25_PAD_A14__A14			0x010 0x230 0x000 0x00 0x000
#define MX25_PAD_A14__GPIO_2_0			0x010 0x230 0x000 0x05 0x000
#define MX25_PAD_A14__SIM1_CLK1			0x010 0x230 0x000 0x06 0x000
#define MX25_PAD_A14__LCDC_SPL			0x010 0x230 0x000 0x07 0x000

#define MX25_PAD_A15__A15			0x014 0x234 0x000 0x00 0x000
#define MX25_PAD_A15__GPIO_2_1			0x014 0x234 0x000 0x05 0x000
#define MX25_PAD_A15__SIM1_RST1			0x014 0x234 0x000 0x06 0x000
#define MX25_PAD_A15__LCDC_PS			0x014 0x234 0x000 0x07 0x000

#define MX25_PAD_A16__A16			0x018 0x000 0x000 0x00 0x000
#define MX25_PAD_A16__GPIO_2_2			0x018 0x000 0x000 0x05 0x000
#define MX25_PAD_A16__SIM1_VEN1			0x018 0x000 0x000 0x06 0x000
#define MX25_PAD_A16__LCDC_REV			0x018 0x000 0x000 0x07 0x000

#define MX25_PAD_A17__A17			0x01c 0x238 0x000 0x00 0x000
#define MX25_PAD_A17__GPIO_2_3			0x01c 0x238 0x000 0x05 0x000
#define MX25_PAD_A17__SIM1_TX			0x01c 0x238 0x554 0x06 0x000
#define MX25_PAD_A17__FEC_TX_ERR		0x01c 0x238 0x000 0x07 0x000

#define MX25_PAD_A18__A18			0x020 0x23c 0x000 0x00 0x000
#define MX25_PAD_A18__GPIO_2_4			0x020 0x23c 0x000 0x05 0x000
#define MX25_PAD_A18__SIM1_PD1			0x020 0x23c 0x550 0x06 0x000
#define MX25_PAD_A18__FEC_COL			0x020 0x23c 0x504 0x07 0x000

#define MX25_PAD_A19__A19			0x024 0x240 0x000 0x00 0x000
#define MX25_PAD_A19__GPIO_2_5			0x024 0x240 0x000 0x05 0x000
#define MX25_PAD_A19__SIM1_RX1			0x024 0x240 0x54c 0x06 0x000
#define MX25_PAD_A19__FEC_RX_ERR		0x024 0x240 0x518 0x07 0x000

#define MX25_PAD_A20__A20			0x028 0x244 0x000 0x00 0x000
#define MX25_PAD_A20__GPIO_2_6			0x028 0x244 0x000 0x05 0x000
#define MX25_PAD_A20__SIM2_CLK1			0x028 0x244 0x000 0x06 0x000
#define MX25_PAD_A20__FEC_RDATA2		0x028 0x244 0x50c 0x07 0x000

#define MX25_PAD_A21__A21			0x02c 0x248 0x000 0x00 0x000
#define MX25_PAD_A21__GPIO_2_7			0x02c 0x248 0x000 0x05 0x000
#define MX25_PAD_A21__SIM2_RST1			0x02c 0x248 0x000 0x06 0x000
#define MX25_PAD_A21__FEC_RDATA3		0x02c 0x248 0x510 0x07 0x000

#define MX25_PAD_A22__A22			0x030 0x000 0x000 0x00 0x000
#define MX25_PAD_A22__GPIO_2_8			0x030 0x000 0x000 0x05 0x000
#define MX25_PAD_A22__SIM2_VEN1			0x030 0x000 0x000 0x06 0x000
#define MX25_PAD_A22__FEC_TDATA2		0x030 0x000 0x000 0x07 0x000

#define MX25_PAD_A23__A23			0x034 0x24c 0x000 0x00 0x000
#define MX25_PAD_A23__GPIO_2_9			0x034 0x24c 0x000 0x05 0x000
#define MX25_PAD_A23__SIM2_TX1			0x034 0x24c 0x560 0x06 0x000
#define MX25_PAD_A23__FEC_TDATA3		0x034 0x24c 0x000 0x07 0x000

#define MX25_PAD_A24__A24			0x038 0x250 0x000 0x00 0x000
#define MX25_PAD_A24__GPIO_2_10			0x038 0x250 0x000 0x05 0x000
#define MX25_PAD_A24__SIM2_PD1			0x038 0x250 0x55c 0x06 0x000
#define MX25_PAD_A24__FEC_RX_CLK		0x038 0x250 0x514 0x07 0x000

#define MX25_PAD_A25__A25			0x03c 0x254 0x000 0x00 0x000
#define MX25_PAD_A25__GPIO_2_11			0x03c 0x254 0x000 0x05 0x000
#define MX25_PAD_A25__FEC_CRS			0x03c 0x254 0x508 0x07 0x000

#define MX25_PAD_EB0__EB0			0x040 0x258 0x000 0x00 0x000
#define MX25_PAD_EB0__AUD4_TXD			0x040 0x258 0x464 0x04 0x000
#define MX25_PAD_EB0__GPIO_2_12			0x040 0x258 0x000 0x05 0x000
#define MX25_PAD_EB0__CSPI3_SS0			0x040 0x258 0x4bc 0x06 0x000

#define MX25_PAD_EB1__EB1			0x044 0x25c 0x000 0x00 0x000
#define MX25_PAD_EB1__AUD4_RXD			0x044 0x25c 0x460 0x04 0x000
#define MX25_PAD_EB1__GPIO_2_13			0x044 0x25c 0x000 0x05 0x000
#define MX25_PAD_EB1__CSPI3_SS1			0x044 0x25c 0x4c0 0x06 0x000

#define MX25_PAD_OE__OE				0x048 0x260 0x000 0x00 0x000
#define MX25_PAD_OE__AUD4_TXC			0x048 0x260 0x000 0x04 0x000
#define MX25_PAD_OE__GPIO_2_14			0x048 0x260 0x000 0x05 0x000

#define MX25_PAD_CS0__CS0			0x04c 0x000 0x000 0x00 0x000
#define MX25_PAD_CS0__GPIO_4_2			0x04c 0x000 0x000 0x05 0x000

Annotation

Atlas domain: Architecture Layer / arch/arm.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.