arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h

File Facts

System: Linux kernel
Corpus path: arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h
Extension: .h
Size: 31739 bytes
Lines: 475
Domain: Architecture Layer
Bucket: arch/arm
Inferred role: Architecture Layer: implementation source
Status: source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __DTS_IMX27_PINFUNC_H
#define __DTS_IMX27_PINFUNC_H

/*
 * The pin function ID is a tuple of
 * <pin mux_id>
 * mux_id consists of
 * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
 *
 * function:      0 - Primary function
 *                1 - Alternate function
 *                2 - GPIO
 * direction:     0 - Input
 *                1 - Output
 * gpio_oconf:    0 - A_IN
 *                1 - B_IN
 *                2 - C_IN
 *                3 - Data Register
 * gpio_iconfa/b: 0 - GPIO_IN
 *                1 - Interrupt Status Register
 *                2 - 0
 *                3 - 1
 *
 * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32
 * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is
 * the pin number on the specific port (between 0 and 31).
 */

#define MX27_PAD_USBH2_CLK__USBH2_CLK                      0x00 0x000
#define MX27_PAD_USBH2_CLK__GPIO1_0                        0x00 0x032
#define MX27_PAD_USBH2_DIR__USBH2_DIR                      0x01 0x000
#define MX27_PAD_USBH2_DIR__GPIO1_1                        0x01 0x032
#define MX27_PAD_USBH2_DATA7__USBH2_DATA7                  0x02 0x004
#define MX27_PAD_USBH2_DATA7__GPIO1_2                      0x02 0x032
#define MX27_PAD_USBH2_NXT__USBH2_NXT                      0x03 0x000
#define MX27_PAD_USBH2_NXT__GPIO1_3                        0x03 0x032
#define MX27_PAD_USBH2_STP__USBH2_STP                      0x04 0x004
#define MX27_PAD_USBH2_STP__GPIO1_4                        0x04 0x032
#define MX27_PAD_LSCLK__LSCLK                              0x05 0x004
#define MX27_PAD_LSCLK__GPIO1_5                            0x05 0x032
#define MX27_PAD_LD0__LD0                                  0x06 0x004
#define MX27_PAD_LD0__GPIO1_6                              0x06 0x032
#define MX27_PAD_LD1__LD1                                  0x07 0x004
#define MX27_PAD_LD1__GPIO1_7                              0x07 0x032
#define MX27_PAD_LD2__LD2                                  0x08 0x004
#define MX27_PAD_LD2__GPIO1_8                              0x08 0x032
#define MX27_PAD_LD3__LD3                                  0x09 0x004
#define MX27_PAD_LD3__GPIO1_9                              0x09 0x032
#define MX27_PAD_LD4__LD4                                  0x0a 0x004
#define MX27_PAD_LD4__GPIO1_10                             0x0a 0x032
#define MX27_PAD_LD5__LD5                                  0x0b 0x004
#define MX27_PAD_LD5__GPIO1_11                             0x0b 0x032
#define MX27_PAD_LD6__LD6                                  0x0c 0x004
#define MX27_PAD_LD6__GPIO1_12                             0x0c 0x032
#define MX27_PAD_LD7__LD7                                  0x0d 0x004
#define MX27_PAD_LD7__GPIO1_13                             0x0d 0x032
#define MX27_PAD_LD8__LD8                                  0x0e 0x004
#define MX27_PAD_LD8__GPIO1_14                             0x0e 0x032
#define MX27_PAD_LD9__LD9                                  0x0f 0x004
#define MX27_PAD_LD9__GPIO1_15                             0x0f 0x032
#define MX27_PAD_LD10__LD10                                0x10 0x004
#define MX27_PAD_LD10__GPIO1_16                            0x10 0x032
#define MX27_PAD_LD11__LD11                                0x11 0x004
#define MX27_PAD_LD11__GPIO1_17                            0x11 0x032
#define MX27_PAD_LD12__LD12                                0x12 0x004
#define MX27_PAD_LD12__GPIO1_18                            0x12 0x032
#define MX27_PAD_LD13__LD13                                0x13 0x004
#define MX27_PAD_LD13__GPIO1_19                            0x13 0x032
#define MX27_PAD_LD14__LD14                                0x14 0x004
#define MX27_PAD_LD14__GPIO1_20                            0x14 0x032
#define MX27_PAD_LD15__LD15                                0x15 0x004
#define MX27_PAD_LD15__GPIO1_21                            0x15 0x032
#define MX27_PAD_LD16__LD16                                0x16 0x004
#define MX27_PAD_LD16__GPIO1_22                            0x16 0x032
#define MX27_PAD_LD17__LD17                                0x17 0x004
#define MX27_PAD_LD17__GPIO1_23                            0x17 0x032
#define MX27_PAD_REV__REV                                  0x18 0x004
#define MX27_PAD_REV__GPIO1_24                             0x18 0x032
#define MX27_PAD_CLS__CLS                                  0x19 0x004
#define MX27_PAD_CLS__GPIO1_25                             0x19 0x032
#define MX27_PAD_PS__PS                                    0x1a 0x004
#define MX27_PAD_PS__GPIO1_26                              0x1a 0x032
#define MX27_PAD_SPL_SPR__SPL_SPR                          0x1b 0x004
#define MX27_PAD_SPL_SPR__GPIO1_27                         0x1b 0x032
#define MX27_PAD_HSYNC__HSYNC                              0x1c 0x004
#define MX27_PAD_HSYNC__GPIO1_28                           0x1c 0x032
#define MX27_PAD_VSYNC__VSYNC                              0x1d 0x004
#define MX27_PAD_VSYNC__GPIO1_29                           0x1d 0x032
#define MX27_PAD_CONTRAST__CONTRAST                        0x1e 0x004
#define MX27_PAD_CONTRAST__GPIO1_30                        0x1e 0x032

Annotation

Atlas domain: Architecture Layer / arch/arm.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.