arch/arm/boot/dts/nxp/imx/imx50-evk.dts
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx50-evk.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/imx/imx50-evk.dts- Extension
.dts- Size
- 2067 bytes
- Lines
- 103
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
imx50.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2013 Greg Ungerer <gerg@uclinux.org>
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
/dts-v1/;
#include "imx50.dtsi"
/ {
model = "Freescale i.MX50 Evaluation Kit";
compatible = "fsl,imx50-evk", "fsl,imx50";
memory@70000000 {
device_type = "memory";
reg = <0x70000000 0x80000000>;
};
};
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi>;
cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>;
status = "okay";
flash: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p32", "jedec,spi-nor";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "bootloader";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "kernel";
reg = <0x100000 0x300000>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
pinctrl_cspi: cspigrp {
fsl,pins = <
MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00
MX50_PAD_CSPI_MISO__CSPI_MISO 0x00
MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00
MX50_PAD_CSPI_SS0__GPIO4_11 0xc4
MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX50_PAD_SSI_RXFS__FEC_MDC 0x80
MX50_PAD_SSI_RXC__FEC_MDIO 0x80
MX50_PAD_DISP_D0__FEC_TX_CLK 0x80
MX50_PAD_DISP_D1__FEC_RX_ERR 0x80
Annotation
- Immediate include surface: `imx50.dtsi`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.