arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi
Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi- Extension
.dtsi- Size
- 3727 bytes
- Lines
- 144
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 DH electronics GmbH
*/
/ {
chosen {
stdout-path = "serial0:115200n8";
};
};
/*
* Special SoM hardware required which uses the pins from micro SD card. The
* pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
* Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
* card must be disabled and the uart1 rts/cts must be output on other DHCOM
* pins, see uart1 and usdhc3 node below.
*/
&can2 {
status = "okay";
};
&gpio1 {
/*
* NOTE: On DRC02, the RS485_RX_En is controlled by a separate
* GPIO line, however the i.MX6 UART driver assumes RX happens
* during TX anyway and that it only controls drive enable DE
* line. Hence, the RX is always enabled here.
*/
rs485-rx-en-hog {
gpio-hog;
gpios = <18 0>; /* GPIO Q */
line-name = "rs485-rx-en";
output-low;
};
};
&gpio3 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "DRC02-In1", "", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H",
"DHCOM-I", "DRC02-HW0", "", "", "", "", "", "",
"", "", "", "", "DRC02-Out1", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio6 {
gpio-line-names =
"", "", "", "DRC02-Out2", "", "", "SOM-HW1", "",
"", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c1 {
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
};
};
&uart1 {
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.