arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi
Extension
.dtsi
Size
2038 bytes
Lines
86
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2021 PHYTEC Messtechnik GmbH
 * Author: Yunus Bas <y.bas@phytec.de>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	reg_wl_en: regulator-wl-en {
		compatible = "regulator-fixed";
		regulator-name = "wlan_en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_wl>;
		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		status = "disabled";
	};
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3_bt>;
	uart-has-rtscts;

	bluetooth {
		compatible = "brcm,bcm43438-bt";
		shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
		device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
		host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
		status = "disabled";
	};
};

&usdhc3 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3_wl>;
	vmmc-supply = <&reg_wl_en>;
	bus-width = <4>;
	non-removable;
	no-1-8-v;
	status = "disabled";

	brmcf: wifi@1 {
		compatible = "brcm,bcm4329-fmac";
		reg = <1>;
	};
};

&iomuxc {
	pinctrl_uart3_bt: uart3-btgrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
			MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
			MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0xb0b1	/* BT ENABLE */
			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0xb0b1	/* DEV WAKEUP */
			MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26	0xb0b1  /* HOST WAKEUP */
		>;
	};

	pinctrl_usdhc3_wl: usdhc3-wlgrp {
		fsl,pins = <

Annotation

Implementation Notes