arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi

Source file repositories/reference/linux-study-clean/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi
Extension
.dtsi
Size
4518 bytes
Lines
143
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <dt-bindings/gpio/gpio.h>
/ {
	clk_brcm: brcm-clock {
		compatible = "gpio-gate-clock";
		#clock-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_microsom_brcm_osc>;
		enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
	};

	reg_brcm: brcm-reg {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio3 19 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_microsom_brcm_reg>;
		regulator-name = "brcm_reg";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <200000>;
	};

	usdhc1_pwrseq: usdhc1_pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>,
			      <&gpio6 0 GPIO_ACTIVE_LOW>;
		clocks = <&clk_brcm>;
		clock-names = "ext_clock";
	};
};

&iomuxc {
	pinctrl_microsom_brcm_bt: microsom-brcm-btgrp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00	0x40013070
			MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01	0x40013070
			MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04	0x40013070
		>;
	};

	pinctrl_microsom_brcm_osc: microsom-brcm-oscgrp {
		fsl,pins = <
			MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05	0x40013070
		>;
	};

	pinctrl_microsom_brcm_reg: microsom-brcm-reggrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x40013070
		>;
	};

	pinctrl_microsom_brcm_wifi: microsom-brcm-wifigrp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K	0x1b0b0
			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x40013070
			MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26	0x40013070
			MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27	0x40013070
		>;
	};

	pinctrl_microsom_uart4: microsom-uart4grp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
			MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
			MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
			MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
		>;
	};

Annotation

Implementation Notes